1. Field of the Invention
The present invention relates to a FIFO (First In First Out) memory control circuit for controlling FIFO memory which is used in various electronic devices. Specifically, the present invention relates to a FIFO memory control circuit capable of performing asynchronous read/write control when a write clock and a read clock are different and it is known or determined which of these clocks has a higher clock frequency.
2. Description of the Related Art
FIG. 11 shows a structure of a conventional FIFO memory control circuit 1100. The FIFO memory control circuit 1100 includes a memory 101, a write control section 102, a read control section 103, a write address circuit 104, a read address circuit 105, and a Full-Empty control circuit 106.
The memory 101 is a dual-port RAM (Random Access Memory) in which reading and writing of data can be performed simultaneously, and which has a memory capacity of N words. In the memory 101, while a write permission signal (WE) is asserted, data (WDATA) is written in an address designated by a write address (WADR) on a word-by-word basis at a clock timing of a write clock signal (WCLK). On the other hand, while a read permission signal (RE) is asserted, data (RDATA) is read from an address designated by a read address (RADR) on a word-by-word basis at a clock timing of a read clock signal (RCLK). The write permission signal (WE) is output from the write control section 102 (described later), and the read permission signal (RE) is output from the read control section 103 (described later).
The write address circuit 104 receives the write clock signal (WCLK) and the write permission signal (WE). While the write permission signal (WE) is asserted, the write address circuit 104 increments the write address (WADR) by one at a clock timing of the write clock signal (WCLK).
The read address circuit 105 receives the read clock signal (RCLK) and the read permission signal (RE). While the read permission signal (RE) is asserted, the read address circuit 105 increments the read address (RADR) by one at a clock timing of the read clock signal (RCLK).
The Full-Empty control circuit 106 is formed by an up-down counter 107 and a signal generator 108. The Full-Empty control circuit 106 obtains the number of effective data, which is the difference between the number of data words written in the memory 101 and the number of data words read from the memory 101. That is, the xe2x80x9cnumber of effective data wordsxe2x80x9d means the number of data words in the memory 101 which have not yet read therefrom. Based on the number of effective data, the Full-Empty control circuit 106 generates control signals for writing and reading operations.
The up-down counter 107 receives the write permission signal (WE) as a count-up enable signal (UPEN) which permits a count-up operation and the read permission signal (RE) as a count-down enable signal (DNEN) which permits a count-down operation. While one of the count-up enable signal (UPEN) and the count-down enable signal (DNEN) is asserted, the up-down counter 107 performs a count operation at a clock timing of the write clock signal (WCLK). A count value (CNT) of the up-down counter 107 is equal to the number of effective data words, which is output to the signal generator 108.
The signal generator 108 receives the count value (CNT) from the up-down counter 107. When the received count value (CNT) is 0, the signal generator 108 outputs to the read control section 103 an empty signal (EMP) which indicates that the memory 101 has no data to be read. When the received count value (CNT) is N (the number of words storable in the memory 101), the signal generator 108 outputs to the write control section 102 a full signal (FLL) which indicates that the memory 101 has no more capacity to store data.
The write control section 102 receives the full signal (FLL). While the full signal (FLL) is asserted, the write control section 102 prohibits writing data in the memory 101, thereby preventing the memory 101 from losing data due to overwriting.
The read control section 103 receives the empty signal (EMP). While the empty signal (EMP) is asserted, the read control section 103 prohibits reading data from the memory 101, thereby preventing one data word from being read twice from the memory 101.
FIG. 12 shows a structure of a conventional FIFO memory control circuit 1200 in which an up-down counter 107xe2x80x2 performs a count operation at a clock timing of a read clock signal (RCLK). In other respects, the FIFO memory control circuit 1200 has the same structure as the conventional FIFO memory control circuit 1100, and descriptions thereof are omitted.
In the conventional FIFO memory control circuit 1100, when the write clock signal (WCLK) and the read clock signal (RCLK) have the same frequency, the up-down counter 107 uses the write permission signal (WE) as a count-up enable signal (UPEN) which permits a count-up operation and the read permission signal (RE) as a count-down enable signal (DNEN) which permits a count-down operation. While one of the count-up enable signal (UPEN) and the count-down enable signal (DNEN) is asserted, the up-down counter 107 performs a count operation at a clock timing of the write clock signal (WCLK). In the conventional FIFO memory control circuit 1200, when the write clock signal (WCLK) and the read clock signal (RCLK) have the same frequency, the up-down counter 107xe2x80x2 uses the write permission signal (WE) as a count-up enable signal (UPEN) which permits a count-up operation and the read permission signal (RE) as a count-down enable signal (DNEN) which permits a count-down operation. While one of the count-up enable signal (UPEN) and the count-down enable signal (DNEN) is asserted, the up-down counter 107xe2x80x2 performs a count operation at a clock timing of the read clock signal (RCLK).
In these conventional FIFO memory control circuits 1100 and 1200, when the write clock signal (WCLK) and the read clock signal (RCLK) have different frequencies, a count operation cannot be correctly performed.
For example, in the conventional FIFO memory control circuit 1100 shown in FIG. 11, the up-down counter 107 performs a count operation at a clock timing of the write clock signal (WCLK). In the case where the write clock signal (WCLK) has a higher frequency than that of the read clock signal (RCLK), as shown in FIG. 13, in one read cycle, the count-down enable signal (DNEN=RE) is asserted for a period longer than one cycle of the write clock signal (WCLK). In such a case, although only one data is actually read out, the count value of the up-down counter 107 may be decremented by 2 or more.
On the other hand, in the conventional FIFO memory control circuit 1200 shown in FIG. 12, the up-down counter 107xe2x80x2 performs a count operation at a clock timing of the read clock signal (RCLK). In the case where the write clock signal (WCLK) has a higher frequency than that of the read clock signal (RCLK), as shown in FIG. 14, although data is actually written in, the count value of the up-down counter 107xe2x80x2 may not be incremented.
Alternatively, when the read clock signal (RCLK) has a higher frequency than that of the write clock signal (WCLK), in the conventional FIFO memory control circuit 1100 shown in FIG. 11, although data is actually read out, the count value of the up-down counter 107 may not be decremented; in the conventional FIFO memory control circuit 1200 shown in FIG. 12, although only one data is actually written in, the count value of the up-down counter 107xe2x80x2 may be incremented by 2 or more.
According to one aspect of the present invention, a FIFO memory control circuit includes: a write address circuit for generating a write address which is an operation address; a read address circuit for generating a read address which is another operation address; a memory which receives a write permission signal, a read permission signal, a write clock signal, and a read clock signal and which has a memory capacity of a predetermined number of words, wherein, while the write permission signal is asserted, data is written into an address in the memory designated by the write address in synchronization with the write clock signal, and while the read permission signal is asserted, data is read from an address in the memory designated by the read address in synchronization with the read clock signal; a first count control enable signal generation circuit for generating a first count control enable signal based on a first clock signal and a least significant bit of a said operation address corresponding to a second clock signal, the first clock signal being one of the write clock signal and the read clock signal which has the higher frequency, and the second clock signal being one of the write clock signal and the read clock signal which has the lower frequency; and an up-down counter which has a count value and receives a count-up enable signal, a count-down enable signal, and the first clock signal, wherein while the count-up enable signal is asserted, the count value is incremented in synchronization with the first clock signal, and while the count-down enable signal is asserted, the count value is decremented in synchronization with the first clock signal, wherein the first count control enable signal is one of the count-up enable signal and the count-down enable signal.
In one embodiment of the present invention, the first clock signal is the write clock signal; the first count control enable signal generation circuit is a count-down enable signal generation circuit; and the first count control enable signal is a count-down enable signal.
In another embodiment of the present invention, the count-down enable signal is asserted for one cycle of the write clock signal in response to one reading operation.
In still another embodiment of the present invention, the first clock signal is the read clock signal; the first count control enable signal generation circuit is a count-up enable signal generation circuit; and the first count control enable signal is a count-up enable signal.
In still another embodiment of the present invention, the count-up enable signal is asserted for one cycle of the read clock signal in response to one writing operation.
In still another embodiment of the present invention, the FIFO memory control circuit further includes a second count control enable signal generation circuit for generating a second count control enable signal based on the first clock signal and a least significant bit of the operation address which corresponds to the first clock signal, wherein the second count control enable signal is the other of the count-up enable signal and the count-down enable signal.
In still another embodiment of the present invention, each of the count-up enable signal and the count-down enable signal is asserted for one cycle of the first clock signal in response to one of a writing operation and a reading operation which corresponds to the first clock signal.
In still another embodiment of the present invention, the FIFO memory control circuit further includes a memory capacity monitoring section, wherein: when the count value of the up-down counter is 0, the memory capacity monitoring section generates an EMPTY signal which indicates that the memory has no data to be read, and when the count value of the up-down counter is equal to the predetermined number of words storable in the memory, the memory capacity monitoring section generates a FULL signal which indicates that the memory has no more capacity to store data.
In still another embodiment of the present invention, the FIFO memory control circuit includes: a write control section for controlling writing of data into the memory based on the FULL signal; and a read control section for controlling reading of data from the memory based on the EMPTY signal.
Hereinafter, functions of the present invention will be described.
According to the present invention, a first count control enable signal is generated based on a first clock signal and a least significant bit of the operation address corresponding to a second clock signal. The first clock signal is one of the write clock signal (WCLK) and the read clock signal (RCLK) having the higher frequency. The second clock signal is one of the write clock signal (WCLK) and the read clock signal (RCLK) having the lower frequency. With such a structure, the first count control enable signal can be asserted in an up-down counter in synchronization with a timing of the first clock signal in response to one reading operation or one writing operation.
Specifically, according to embodiment 1 of the present invention, in the case where the frequency of the write clock signal (WCLK) is higher than that of the read clock signal (RCLK), a count-down enable signal generation circuit generates a count-down enable signal (DNEN) based on a least significant bit (RADR0) of the read address (RADR) and the write clock signal (WCLK). As a result, the count-down enable signal (DNEN) is asserted in the up-down counter in synchronization with a timing of the write clock signal (WCLK) in response to one reading operation.
While the count-down enable signal (DNEN) is asserted in the up-down counter, the up-down counter performs a count-down operation (decrementation) in synchronization with the write clock signal (WCLK). Thus, the up-down counter can decrement the count value (CNT) once in response to one reading operation. While the write permission signal (WE) is asserted in the up-down counter, the up-down counter performs a count-up operation (incrementation) using the write permission signal (WE) as a count-up enable signal (UPEN) in synchronization with the write clock signal (WCLK). Thus, the count value (CNT) can be incremented once in response to one writing operation.
The count-down enable signal (DNEN) only needs to be asserted for one cycle of the write clock signal (WCLK).
Specifically, according to embodiment 2 of the present invention, in the case where the frequency of the read clock signal (RCLK) is higher than that of the write clock signal (WCLK), a count-up enable signal generation circuit generates a count-up enable signal (UPEN) based on a least significant bit (WADR0) of the write address (WADR) and the read clock signal (RCLK). As a result, the count-up enable signal (UPEN) is asserted in the up-down counter in synchronization with a timing of the read clock signal (RCLK) in response to one writing operation.
While the count-up enable signal (UPEN) is asserted in the up-down counter, the up-down counter performs a count-up operation (incrementation) in synchronization with the read clock signal (RCLK). Thus, the up-down counter can increment the count value (CNT) once in response to one writing operation. While the read permission signal (RE) is asserted in the up-down counter, the up-down counter performs a count-down operation (decrementation) using the read permission signal (RE) as a count-down enable signal (DNEN) in synchronization with the read clock signal (RCLK). Thus, the count value (CNT) can be decremented once in response to one reading operation.
The count-up enable signal (UPEN) only needs to be asserted for one cycle of the read clock signal (RCLK).
Specifically, according to embodiment 3 of the present invention, a count-down enable signal generation circuit generates a count-down enable signal (DNEN) based on a least significant bit (RADR0) of the read address (RADR) and one of a write clock signal (WCLK) and a read clock signal (RCLK) having the higher frequency. As a result, the count-down enable signal (DNEN) is asserted in the up-down counter in response to one reading operation in synchronization with a timing of one of the write clock signal (WCLK) and the read clock signal (RCLK) having the higher frequency. On the other hand, a count-up enable signal generation circuit generates a count-up enable signal (UPEN) based on a least significant bit (WADR0) of the write address (WADR) and one of the write clock signal (WCLK) and the read clock signal (RCLK) having the higher frequency. As a result, the count-up enable signal (UPEN) is asserted in the up-down counter in response to one writing operation in synchronization with a timing of one of the write clock signal (WCLK) and the read clock signal (RCLK) having the higher frequency. While the count-down enable signal (DNEN) is asserted in the up-down counter, the up-down counter performs a count-down operation (decrementation) in synchronization with one of the write clock signal (WCLK) and the read clock signal (RCLK) having the higher frequency. Thus, the up-down counter can decrement the count value (CNT) once in response to one reading operation. While the count-up enable signal (UPEN) is asserted in the up-down counter, the up-down counter performs a count-up operation (incrementation) in synchronization with one of the write clock signal (WCLK) and the read clock signal (RCLK) having the higher frequency. Thus, the up-down counter can increment the count value (CNT) once in response to one writing operation.
Each of the count-down enable signal (DNEN) and the count-up enable signal (UPEN) only needs to be asserted for one cycle of one of a write clock signal (WCLK) and a read clock signal (RCLK) having the higher frequency.
When the count value (CNT) of the up-down counter is 0, a memory capacity monitoring section generates an empty signal (EMP), and a read control section controls reading of data from the memory based on the empty signal (EMP). On the other hand, when the count value (CNT) of the up-down counter is equal to the predetermined number of words storable in the memory, the memory capacity monitoring section generates a FULL signal (FLL), and a write control section controls writing of data into the memory based on the FULL signal (FLL).
According to the present invention, the up-down counter can correctly count the amount of effective data in the memory. Thus, data in the memory can be prevented from being lost by being overwritten, and data in the memory can be prevented from being read out twice.
Thus, the invention described herein makes possible the advantage of providing a FIFO memory control circuit in which the amount of effective data in a memory can be correctly counted so that when the frequencies of a read clock and a write clock are different, data is prevented from being lost by being overwritten, and data is prevented from being read out twice.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.